3 / 28 page
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Document Number: 38-05622 Rev. *C
Page 3 of 28
Logic Block Diagram (CY7C1319BV18)
1M x 18 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
36
18
72
18
BWS[1:0]
VREF
Write
Reg
36
20
C
C
Write
Reg
Write
Reg
Write
Reg
18
LD
Control
Burst
Logic
A(1:0)
A(19:2)
18
CQ
CQ
2
R/W
DOFF
Logic Block Diagram (CY7C1321BV18)
512K x 36 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
72
36
144
36
BWS[3:0]
VREF
Write
Reg
72
19
C
C
Write
Reg
Write
Reg
Write
Reg
36
LD
Control
Burst
Logic
A(1:0)
A(18:2)
17
CQ
CQ
2
R/W
DOFF