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CY7C1354A
CY7C1356A
Document #: 38-05161Rev. *E
Page 2 of 28
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Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
DQa, DQb
CLK
Input
Registers
Mux
Output Registers
Output Buffers
Address
Control
Sel
Control Logic
OE#
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
CE#, CE2#, CE2
SA0, SA1, SA
OE
CEN
ADV/LD
WEN
BWa, BWb
CE, CE2, CE3
CEN
A0, A1, A
Functional Block Diagram—256K × 36[1]
DQa-DQd
CLK
Input
Registers
Mux
Output Registers
Output Buffers
Address
Control
Sel
Control Logic
OE#
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
BWc#, BWd#
CE#, CE2#, CE2
SA0, SA1, SA
Functional Block Diagram—512K × 18[1]
CEN
ADV/LD
WEN
BWa, BWb,
CE, CE2, CE3
CEN
BWc, BWd
OE
A0, A1, A