CY7C1348G-166AXI datasheet(11/16 Pages) CYPRESS

Part #	CY7C1348G-166AXI

Description	4-Mbit (128K x 36) Pipelined DCD Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 16 page

CY7C1348G

Document #: 38-05608 Rev. *D

Page 11 of 16

Switching Waveforms

Read Timing[17]

Note:

17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

OE

ADSC

CE

tAH

tAS

A1

tCEH

tCES

GW, BWE,BW

Data Out (Q)

High-Z

tDOH

tCO

ADV

tOEHZ

tCO

Single READ

BURST READ

tOEV

tOELZ

tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A3)

Q(A2 + 3)

A2

A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE

UNDEFINED

[A:D]

CLZ

t

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