PRELIMINARY
CY7C1317AV18
CY7C1319AV18
CY7C1321AV18
Document #: 38-05500 Rev. *B
Page 10 of 20
Capacitance[16]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range [17, 18]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min. Max. Min. Max. Min. Max.
tCYC
tKHKH
K Clock and C Clock Cycle Time
4.0
6.3
5.0
7.9
6.0
8.4
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
1.6
–
2.0
–
2.4
–
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising
edge to rising edge)
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to ris-
ing edge)
0.0
1.8
0.0
2.3
0.0
2.8
ns
Set-up Times
tSA
tSA
Address Set-up to K Clock Rise
0.5
–
0.6
–
0.7
–
ns
tSC
tSC
Control Set-up to Clock (K, K) Rise (LD, R/W)
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tSC
Double Data Rate Control Set-up to Clock (K, K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.35
–
0.4
–
0.5
–
ns
tSD
tSD
D[X:0] Set-up to Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.5
–
0.6
–
0.7
–
ns
tHC
tHC
Control Hold after Clock (K and K) Rise (LD, R/W)
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tHC
Double Data Rate Control Hold after Clock (K and K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.35
–
0.4
–
0.5
–
ns
tHD
tHD
D[X:0] Hold after Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Notes:
17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
1.25V
0.25V
R = 50
Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
RL = 50Ω
Z0 = 50Ω
VREF = 0.75V
VREF = 0.75V
[15]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
RQ =
250
Ω
(b)
RQ =
250
Ω
Slew Rate = 2V/ns
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