CY7C1316JV18 datasheet(23/26 Pages) CYPRESS

Part #	CY7C1316JV18

Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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23 / 26 page

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Document Number: 001-15271 Rev. *B

Page 23 of 26

Switching Waveforms

Figure 3. Read/Write/Deselect Sequence [24, 25, 26]

READ

NOP

WRITE

NOP

1

23

4

5

6

7

8

9

10

Q40

t

KHCH

tCO

t

tHC

t

tHA

tSD

tHD

tKHCH

tSD

tHD

DON’T CARE

UNDEFINED

tCLZ

tDOH

tCHZ

SC

tKH

tKHKH

tKL

tCYC

A0

D20

D21

D30

D31

Q00

Q11

Q01

Q10

A1

A2

A3

A4

Q41

tCCQO

tCQOH

tCCQO

tCQOH

tKL

tCYC

K

LD

R/W

A

DQ

C

C#

CQ

CQ#

SA

tKH

tKHKH

tCQD

tCQDOH

tCQH

tCQHCQH

Notes

24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

25. Outputs are disabled (High-Z) one clock cycle after a NOP.

26. In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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CY7C1316JV18 Datasheet(PDF) 23 Page - Cypress Semiconductor

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