PRELIMINARY
CY7C1304CV25
Document #: 38-05494 Rev. *A
Page 4 of 18
will be valid 2.5 ns from the rising edge of the output clock (C
and C, or K and K when in single clock mode, 167-MHz
device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes 2 clock cycles to
complete. Therefore, Read accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C, or K and K when in single clock mode).
When the read port is deselected, the CY7C1304CV25 will
first complete the pending read transactions. Synchronous
internal circuitry will automatically three-state the outputs
following the next rising edge of the positive output clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
negative input clock (K) the information presented to D[17:0] is
also stored into the Write Data Register provided BWS[1:0] are
both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans-
ferred into the device on every rising edge of the input clocks
(K and K).
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1304CV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS0 and BWS1 which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
De-asserting the Byte Write Select input during the data
portion of a write will allow the data stored in the device for that
byte to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1304CV25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1304CV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Depth Expansion
The CY7C1304CV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
