PRELIMINARY
CY7C1305AV18
CY7C1307AV18
Document #: 38-05495 Rev. *A
Page 6 of 20
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7, 8, 9]
Operation
K
RPS
WPS
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
wait one cycle; input write data on two
consecutive K and K rising edges.
L-H
H[8]
L[9]
D(A+00)at
K(t+1)
↑
D(A+01) at
K(t+1)
↑
D(A+10) at
K(t+2)
↑
D(A+11) at
K(t+2)
↑
Read Cycle:
Load address on the rising edge of K;
wait one cycle; read data on two
consecutive C and C rising edges.
L-H
L[9]
X
Q(A+00) at
C(t+1)
↑
Q(A+01) at
C(t+1)
↑
Q(A+10) at
C(t+2)
↑
Q(A+11) at
C(t+2)
↑
NOP: No operation
L-H
H
H
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock stopped
Stopped
X
X
Previous state Previous state Previous state Previous state
Write Cycle Descriptions (CY7C1305AV18)[2,10]
BWS0
BWS1
KK
Comments
L
L
L-H
-
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L
L
-
L-H
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L
H
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] will remain unaltered.
L
H
-
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] will remain unaltered.
H
L
L-H
-
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the
device. D[8:0] will remain unaltered.
H
L
-
L-H
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the
device. D[8:0] will remain unaltered.
H
H
L-H
-
No data is written into the device during this portion of a Write operation.
H
H
-
L-H
No data is written into the device during this portion of a Write operation.
Notes:
1. The above application shows four QDR-I being used.
2. X = Don't Care, H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read request.
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 in the case of CY7C1305AV18 and BWS2 and BWS3 in
the case of CY7C1307AV18 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
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