PRELIMINARY
9-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture
CY7C1304CV25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05494 Rev. *A
Revised June 1, 2004
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165-ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG 1149.1 compatible test access port
Configurations
CY7C1304CV25 – 512K x 18
Functional Description
The CY7C1304CV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated Data Outputs to support Read operations
and the Write port has dedicated Data Inputs to support Write
operations. QDR architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Access to
each port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
device’s Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 18-bit
words. Since data can be transferred into and out of the device
on every rising edge of both input clock (K/K and C/C) memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1304CV25)
CLK
A(16:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
17
18
72
18
BWS[0:1]
Vref
Write
Reg
36
A(16:0)
17
C
C
Write
Reg
Write
Reg
Write
Reg
18
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