PRELIMINARY
CY7C1303AV25
CY7C1306AV25
Document #: 38-05493 Rev. *A
Page 3 of 19
Pin Configuration - CY7C1306AV25 (Top View)
1
2
3
456789
10
11
A
NC
Gnd/
288M
NC/ 72M
WPS
BWS2
K
BWS1
RPS
NC/36M
Gnd/
144M
NC
B
Q27
Q18
D18
A
BWS3
KBWS0
AD17
Q17
Q8
C
D27
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
AAA
TMS
TDI
Pin Definitions
Name
I/O
Description
D[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1303AV25 – D[17:0]
CY7C1306AV25 – D[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When as-
serted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations.
CY7C1303AV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1306AV25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the cor-
responding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read opera-
tions and on the rising edge of K for Write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 1M x
18 (2 arrays each of 512K x 18) for CY7C1303AV25 and 512K x 36 (2 arrays each of
256K x 36) for CY7C1306AV25. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1303AV25 and 18 address inputs for CY7C1306AV25.
These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically three-stated.
CY7C1303AV25 - Q[17:0]
CY7C1306AV25 - Q[35:0]
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the K clock. Each
read access consists of a burst of two sequential 18-bit or 36-bit transfers.
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