DS14285/DS14287

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DETAILED DESCRIPTION

The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287

clock function with the additional feature of providing nonvolatile control for an external SRAM.

Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt,

square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy

source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package.

The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external

to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load

please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”

The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard

CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287

battery.

For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when

Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the

DS14285/DS14287. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15

internal divider stages of the real time clock. The frequency of the SQW pin can be changed by

programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE

AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because

address information and data information time-share the same signal paths. The addresses are present

during the first portion of the bus cycle and the same pins and signal paths are used for data in the second

portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287

since the bus change from address to data occurs during the internal RAM access time. Addresses must be

valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from

pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or

RD

pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions