PRELIMINARY
CY7C1071AV33
Document #: 38-05634 Rev. *A
Page 4 of 10
AC Test Loads and Waveforms[3]
AC Switching Characteristics Over the Operating Range [4]
Parameter
Description
-10
-12
Unit
Min.
Max.
Min.
Max.
Read Cycle
tpower
VCC(typical) to the first access
[5]
11
ms
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
10
12
ns
tOHA
Data Hold from Address Change
3
3
ns
tACE
CE HIGH to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
tLZOE
OE LOW to Low-Z
1
1
ns
tHZOE
OE HIGH to High-Z[6]
56
ns
tLZCE
CE HIGH to Low-Z[6]
33
ns
tHZCE
CE LOW to High-Z[6]
56
ns
tPU
CE HIGH to Power-Up[7]
00
ns
tPD
CE LOW to Power-Down[7]
10
12
ns
tDBE
Byte Enable to Data Valid
10
12
ns
tLZBE
Byte Enable to Low-Z
1
1
ns
tHZBE
Byte Disable to High-Z
5
6
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
10
12
ns
tSCE
CE HIGH to Write End
7
8
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified
otherwise.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200
mV from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE HIGH and WE LOW. Chip enables must be active and WE and byte enables must be LOW
to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading
edge of the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317
Ω
R2
351
Ω
Rise time > 1 V/ns
Fall time:
> 1 V/ns
(c)
OUTPUT
50
Ω
Z0 = 50Ω
VTH = 1.5V
30 pF*
* Capacitive Load consists of all
components of the test environment.
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