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PRELIMINARY
CY7C1071AV33
Document #: 38-05634 Rev. *A
Page 5 of 10
tAW
Address Set-up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5.5
6
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low-Z[6]
33
ns
tHZWE
WE LOW to High-Z[6]
56
ns
tBW
Byte Enable to End of Write
7
8
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[11]
Min.
Max
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
Com’l / Ind’l
VCC = VDR = 2.0V,
CE < 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
100
mA
tCDR
[2]
Chip Deselect to Data Retention Time
0
ns
tR
[10]
Operation Recovery Time
μs
AC Switching Characteristics Over the Operating Range (continued)[4]
Parameter
Description
-10
-12
Unit
Min.
Max.
Min.
Max.
Data Retention Waveform
3.0V
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
VCC
CE
Switching Waveforms
Read Cycle No. 1[11, 13]
Notes:
10. Test conditions assume tf < 3 ns.
11. No input may exceed VCC + 0.3V.
12. Device is continuously selected. OE, BHE and/or BHE = VIL. CE = VIH.
13. WE is HIGH for Read cycle.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
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