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CY7C1062DV33
Document Number: 38-05477 Rev.*D
Page 4 of 11
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
pF
COUT
IO Capacitance
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
119-Ball
PBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
20.31
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
8.35
°C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows. [4]
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
(a)
(b)
R1 317
Ω
R2
351
Ω
Fall Time:> 1V/ns
(c)
OUTPUT
50
Ω
Z0= 50Ω
VTH = 1.5V
30 pF*
*Capacitive Load consists of all
components of the test environment
Rise Time > 1V/ns
*Including jig
and scope
Note
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
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