CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 38-05132 Rev. *I
Revised January 04, 2008
Features
■ Temperature ranges
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■ Pin and function compatible with CY7C1021BV33
■ High speed
❐ tAA = 8 ns (Commercial)
❐ tAA = 10 ns (Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■ CMOS for optimum speed and power
■ Low active power: 325 mW (max)
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from IO pins (IO1 through IO8), is written into the
location specified on the address pins (A0 through A15). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO9 through
IO16) is written into the location specified on the address pins (A0
through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO1 to IO8. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO9 to IO16. For more information, see the
“Truth Table” on page 9 for a complete description of Read and
Write modes.
The input and output pins (IO1 through IO16) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
64K x 16
RAM Array
IO0–IO7
A7
A6
A5
A4
A3
A0
COLUMN DECODER
DATA IN DRIVERS
OE
A2
A1
IO8–IO15
CE
WE
BLE
BHE
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