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CY7C1024DV33
Document Number: 001-08353 Rev. *B
Page 6 of 9
Switching Waveforms
Figure 2. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
Figure 3. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
Figure 4. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
PREVIOUS DATA VALID
DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
WE
DATA IO
ADDRESS
Notes
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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