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CY7C144
CY7C145
Document #: 38-06034 Rev. *C
Page 9 of 20
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[21, 23, 24]
Notes:
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
pulse can be as short as the specified tPWE.
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during write.
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
t
LZOE
SEM OR CE
R/W
ADDRESS
OE
DATA OUT
DATA IN
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
SEM OR CE
R/W
ADDRESS
DATA OUT
DATA IN
tLZWE
DATAVALID
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