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CY7C1020CV26 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY7C1020CV26
Description  512Kb (32K x 16) Static RAM
Download  8 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1020CV26 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C1020CV26
Document #: 38-05406 Rev. *A
Page 3 of 8
AC Test Loads and Waveforms[4]
AC Switching Characteristics Over the Operating Range
Parameter
Description
CY7C1020CV26
Unit
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
ns
tAA
Address to Data Valid
15
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
15
ns
tDOE
OE LOW to Data Valid
7
ns
tLZOE
OE LOW to Low Z[5]
0
ns
tHZOE
OE HIGH to High Z[5, 6]
7
ns
tLZCE
CE LOW to Low Z[5]
3
ns
tHZCE
CE HIGH to High Z[5, 6]
7
ns
tPU
[7]
CE LOW to Power-up
0
ns
tPD
[7]
CE HIGH to Power-down
15
ns
tDBE
Byte Enable to Data Valid
7
ns
tLZBE
Byte Enable to Low Z
0
ns
tHZBE
Byte Disable to High Z
7
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Set-Up to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
10
ns
tSD
Data Set-Up to Write End
8
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[5]
3
ns
tHZWE
WE LOW to High Z[5, 6]
4
ns
tBW
Byte Enable to End of Write
10
ns
Notes:
4. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.5V and transmission line loads as in
(a) of AC Test Loads.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. This parameter is guaranteed by design and is not tested.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
90%
10%
2.5V
GND
90%
10%
ALL INPUT PULSES
Rise Time: 1 V/ns
Fall Time:1 V/ns
2.6V
OUTPUT
30 pF
R 1830 Ω
R2
1976 Ω
(a)
(b)


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