CY7C344
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Document #: 38-03006 Rev. *B
Page 4 of 15
External Synchronous Switching Characteristics Over Operating Range [7]
Parameter
Description
7C344-15
7C344-20
7C344-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPD1
Dedicated Input to Combinatorial Output Delay[8] Com’l/Ind
15
20
25
ns
Mil
15
20
25
tPD2
I/O Input to Combinatorial Output Delay[9]
Com’l/Ind
15
20
25
ns
Mil
15
20
25
tPD3
Dedicated Input to Combinatorial Output Delay
with Expander Delay[10]
Com’l/Ind
30
30
40
ns
Mil
30
30
40
tPD4
I/O Input to Combinatorial Output Delay with
Expander Delay[4, 11]
Com’l/Ind
30
30
40
ns
Mil
30
30
40
tEA
Input to Output Enable Delay[4]
Com’l/Ind
20
20
25
ns
Mil
20
20
25
tER
Input to Output Disable Delay[4]
Com’l/Ind
20
20
25
ns
Mil
20
20
25
tCO1
Synchronous Clock Input to Output Delay
Com’l/Ind
10
12
15
ns
Mil
10
12
15
tCO2
Synchronous Clock to Local Feedback to
Combinatorial Output[4, 12]
Com’l/Ind
20
22
29
ns
Mil
20
22
29
tS
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input
Com’l/Ind
10
12
15
ns
Mil
10
12
15
tH
Input Hold Time from Synchronous Clock Input[7] Com’l/Ind
0
0
0
ns
Mil
0
0
0
tWH
Synchronous Clock Input HIGH Time[4]
Com’l/Ind
6
7
8
ns
Mil
6
7
8
tWL
Synchronous Clock Input LOW Time[4]
Com’l/Ind
6
7
8
ns
Mil
6
7
8
tRW
Asynchronous Clear Width[4]
Com’l/Ind
20
20
25
ns
Mil
20
20
25
tRR
Asynchronous Clear Recovery Time[4]
Com’l/Ind
20
20
25
ns
Mil
20
20
25
tRO
Asynchronous Clear to Registered Output
Delay[4]
Com’l/Ind
15
20
25
ns
Mil
15
20
25
tPW
Asynchronous Preset Width[4]
Com’l /Ind
20
20
25
ns
Mil
20
20
25
tPR
Asynchronous Preset Recovery Time[4]
Com’l /Ind
20
20
25
ns
Mil
20
20
25
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for
which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register
is synchronously clocked. This parameter is tested periodically by sampling production material.
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