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D1340-33 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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D1340-33 Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 14 page I2C Serial Data Bus The DS1340 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiv- ing data as a receiver. The device that controls the message is called a master. The devices that are con- trolled by the master are slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP condi- tions must control the bus. The DS1340 operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications a standard mode (100kHz max clock rate) and a fast mode (400kHz max clock rate) are defined. The DS1340 works in both modes. The following bus protocol has been defined (Figure 7): • Data transfer can be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are inter- preted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. START data transfer: A change in the data line’s state from high to low, while the clock line is high, defines a START condition. STOP data transfer: A change in the data line’s state from low to high, while the clock line is high, defines a STOP condition. Data valid: The data line’s state represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condi- tion and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowl- edge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. I2C RTC with Trickle Charger ____________________________________________________________________ 11 STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED ACK START CONDITION ACK ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SLAVE ADDRESS MSB SCL SDA R/W DIRECTION BIT 12 6 7 8 9 1 2 8 9 3–7 Figure 7. I2C Data Transfer Overview |
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