CY7C145-35JI datasheet(10/20 Pages) CYPRESS

Part #	CY7C145-35JI

Description	8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C144

CY7C145

Document #: 38-06034 Rev. *C

Page 10 of 20

Semaphore Read After Write Timing, Either Side[25]

Semaphore Contention[26, 27, 28]

Notes:

25. CE = HIGH for the duration of the above timing (both write and read cycle).

26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH

27. Semaphores are reset (available to both ports) at cycle start.

28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.

Switching Waveforms (continued)

tSOP

tAA

SEM

R/W

OE

I/O0

VALID ADDRESS

tHD

DATA IN VALID

DATA OUT VALID

tOHA

A0−A 2

tAW

tHA

tACE

tSOP

tSCE

tSD

tSA

tPWE

tSWRD

tDOE

WRITE CYCLE

READ CYCLE

MATCH

tSPS

A0L−A 2L

MATCH

R/WL

SEML

A0R−A 2R

R/WR

SEMR

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