1K x 8 Dual-Port Static RAM
CY7C130/CY7C131
CY7C140/CY7C141
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-06002 Rev. *D
Revised August 29, 2005
Features
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC,
52-Pin TQFP.
• Pb-Free packages available
Functional Description
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. INT is an interrupt flag indicating
that data has been placed in a unique location (3FF for the left
port and 3FE for the right port). An automatic power-down
feature is controlled independently on each port by the chip
enable (CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin
Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP.
Note:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required.
Logic Block Diagram
Pin Configurations
13
14
15
16
17
18
19
20
21
22
23
26
27
28
32
31
30
29
33
36
35
34
24
25
GND
1
2
3
4
5
6
7
8
9
10
11
38
39
40
44
43
42
41
45
48
47
46
12
37
R/W L
CEL
BUSY L
INTL
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
CER
R/WR
BUSYR
INTR
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
VCC
DIP
Top View
7C130
7C140
R/WL
BUSYL
CEL
OEL
A 9L
A 0L
A 0R
A 9R
R/WR
CER
OER
CER
OER
CEL
OEL
R/WL
R/WR
I/O7L
I/O0L
I/O7R
I/O0R
BUSYR
INTL
INTR
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[1]
[2]
[2]
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