PRELIMINARY
64K (8K x 8) Static RAM
CY7C185D
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05466 Rev. *C
Revised January 10, 2005
Features
• Pin- and function-compatible with CY7C185
•High speed
—tAA = 10 ns
• Low active power
—ICC = 60 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 3 mA
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Lead (Pb)-Free Packages
Functional Description[1]
The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
256 x 32 x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
POWER
DOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE1
CE2
WE
OE
Top View
DIP/SOJ/SOIC
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