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CY7C150-12SC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C150-12SC
Description  1Kx4 Static RAM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C150-12SC Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C150
Document #: 38-05024 Rev. *A
Page 3 of 11
Switching Characteristics Over the Operating Range[2,5]
Parameter
Description
7C150
−10
7C150
−12
7C150
−15
7C150
−25
7C150
−35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
10
12
15
25
35
ns
tAA
Address to Data Valid
10
12
15
25
35
ns
tOHA
Output Hold from Address
Change
2
2
2
2
2
ns
tACS
CS LOW to Data Valid
8
10
12
15
20
ns
tLZCS
CS LOW to Low Z[6]
0
0
0
0
0
ns
tHZCS
CS HIGH to High Z[6,7]
6
8
11
20
25
ns
tDOE
OE LOW to Data Valid
6
8
10
15
20
ns
tLZOE
OE LOW to Low Z[6]
0
0
0
0
0
ns
tHZOE
OE HIGH to High Z[6,7]
6
8
9
20
25
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
10
12
15
25
35
ns
tSCS
CS LOW to Write End
6
8
11
15
20
ns
tAW
Address Set-Up to Write End
8
10
13
20
30
ns
tHA
Address Hold from Write End
2
2
2
5
5
ns
tSA
Address Set-Up to Write Start
2
2
2
5
5
ns
tPWE
WE Pulse Width
6
8
11
15
20
ns
tSD
Data Set-Up to Write End
6
8
11
15
20
ns
tHD
Data Hold from Write End
2
2
2
5
5
ns
tLZWE
WE HIGH to Low Z[6]
0
0
0
0
0
ns
tHZWE
WE LOW to High Z[6,7]
6
8
12
20
25
ns
RESET CYCLE
tRRC
Reset Cycle Time
20
24
30
50
70
ns
tSAR
Address Valid to Beginning of
Reset
0
0
0
0
0
ns
tSWER
Write Enable HIGH to Beginning
of Reset
0
0
0
0
0
ns
tSCSR
Chip Select LOW to Beginning of
Reset
0
0
0
0
0
ns
tPRS
Reset Pulse Width
10
12
15
20
30
ns
tHCSR
Chip Select Hold After End of
Reset
0
0
0
0
0
ns
tHWER
Write Enable Hold After End of
Reset
8
12
15
30
40
ns
tHAR
Address Hold After End of Reset
10
12
15
30
40
ns
tLZRS
Reset HIGH to Output in Low Z[6]
0
0
0
0
0
ns
tHZRS
Reset LOW to Output in
High Z[6,7]
6
8
12
20
25
ns
Notes:
5.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6.
At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
7.
tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.


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