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CY7C150
Document #: 38-05024 Rev. *A
Page 5 of 11
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
Switching Waveforms (continued)
Write Cycle No.2(CS Controlled)
tWC
DATA UNDEFINED
HIGH IMPEDANCE
tSCS
tAW
tSA
tPWE
tHA
tHD
tHZWE
tSD
ADDRESS
CE
WE
DATA IN
DATA I/O
C150-8
DATA IN VALID
[8,12]
Reset Cycle
tRRC
OUTPUT VALID ZERO
tSAR
tHCSR
tHAR
tLZRS
ADDRESS
WE
CS
DATA I/O
C150-9
tPRS
HIGH
IMPEDANCE
tHZRS
tSWER
tSCSR
RESET
tHWER
[13]
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