DS1337 I

3 of 15

AC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Fast mode

100

400

SCL Clock Frequency

Standard mode

0

100

kHz

Fast mode

1.3

Bus Free Time Between a

STOP and START Condition

Standard mode

4.7

µs

Fast mode

0.6

Hold Time (Repeated)

START Condition (Note 10)

Standard mode

4.0

µs

Fast mode

1.3

LOW Period of SCL Clock

Standard mode

4.7

µs

Fast mode

0.6

HIGH Period of SCL Clock

Standard mode

4.0

µs

Fast mode

0.6

Setup Time for a Repeated

START Condition

Standard mode

4.7

µs

Fast mode

0

0.9

Data Hold Time

(Notes 11, 12)

Standard mode

0

µs

Fast mode

100

Data Setup Time (Note 13)

Standard mode

250

ns

Fast mode

300

Rise Time of Both SDA and

SCL Signals (Note 14)

Standard mode

1000

ns

Fast mode

300

Fall Time of Both SDA and

SCL Signals (Note 14)

Standard mode

300

ns

Fast mode

0.6

Setup Time for STOP

Condition

Standard mode

4.0

µs

Capacitive Load for Each Bus

Line

(Note 14)

400

pF

I/O Capacitance (SDA, SCL)

(Note 15)

10

pF

Note 1:

Limits at -40°C are guaranteed by design and are not production tested.

Note 2:

SCL only.

Note 3:

SDA,

INTA, and SQW/INTB.

Note 4:

Note 5:

Specified with the I

Note 6:

SQW enabled.

Note 7:

Specified with the SQW function disabled by setting INTCN = 1.

Note 8:

Using recommended crystal on X1 and X2.

Note 9:

The device is fully accessible when 1.8

≤ V

Note 10:

After this period, the first clock pulse is generated

Note 11:

bridge the undefined region of the falling edge of SCL.

Note 12:

Note 13:

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

line is released.

Note 14:

Note 15:

Guaranteed by design. Not production tested.