3 / 20 page
CY7C144
CY7C145
Document #: 38-06034 Rev. *C
Page 3 of 20
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
80-Pin TQFP
Top View
/O 2L
/O 3L
/O 4L
/O 5L
/O 6L
/O 7L
VCC
GND
/O0R
/O1R
2R
O 3R
O 4R
5R
GND
V CC
A5L
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
M/S
A0R
A1R
A2R
A3R
A4R
INTL
O 6R
CY7C145
BUSYR
INTR
NC
NC
NC
NC
NC
/O
O
NC
Pin Definitions
Left Port
Right Port
Description
I/O0L−7L(8L) I/O0R−7R(8R) Data bus Input/Output
A0L−12L
A0R−12R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
SEML
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-
icant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads
location 1FFF.
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
Selection Guide
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Maximum Access Time
15
25
35
55
ns
Maximum Operating Current
220
180
160
160
mA
Maximum Standby Current for ISB1
60
40
30
30
mA