CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *H
Page 10 of 19
Data Retention Mode
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0V).
Notes:
24. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
25. Test conditions used are Load 2.
26. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
27. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
tSD
Data Set-up to Write End
15
15
ns
tHD
Data Hold From Write End
0
0
ns
tHZWE
[22, 23]
R/W LOW to High Z
12
15
ns
tLZWE
[22, 23]
R/W HIGH to Low Z
3
0
ns
tWDD
[24]
Write Pulse to Data Delay
45
50
ns
tDDD
[24]
Write Data Valid to Read Data Valid
30
35
ns
Busy Timing[25]
tBLA
BUSY LOW from Address Match
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
20
20
ns
tBLC
BUSY LOW from CE LOW
20
20
ns
tBHC
BUSY HIGH from CE HIGH
17
17
ns
tPS
Port Set-up for Priority
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
17
ns
tBDD
[26]
BUSY HIGH to Data Valid
20
25
ns
Interrupt Timing[25]
tINS
INT Set Time
20
20
ns
tINR
INT Reset Time
20
20
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)10
12
ns
tSWRD
SEM Flag Write to Read Time
5
5
ns
tSPS
SEM Flag Contention Window
5
5
ns
tSAA
SEM Address Access Time
20
25
ns
Switching Characteristics Over the Operating Range (continued)[19]
Parameter
Description
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Unit
-20
-25
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[27]
Max.
Unit
ICCDR1
@ VCCDR = 2V
50
μA
Data Retention Mode
3.0V
3.0V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
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