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CY7C138-25JXC Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C138-25JXC
Description  4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C138-25JXC Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY7C138
CY7C139
Document #: 38-06037 Rev. *B
Page 10 of 16
Busy Timing Diagram No. 1 (CE Arbitration)[30]
Busy Timing Diagram No. 2 (Address Arbitration)[30]
Note:
30. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC
tBHC
ADDRESS MATCH
tPS
tBLC
tBHC
ADDRESSL,R
BUSYR
CEL
CER
BUSY L
CER
CEL
ADDRESSL,R
CEL Valid First:
CER Valid First:
ADDRESS MATCH
tPS
ADDRESS L
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA
tBHA
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
BUSY L
tRC or tWC
tBLA
tBHA
ADDRESSR
Left Address Valid First:
Right Address Valid First:


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