CY7C056V
CY7C057V
Document #: 38-06055 Rev. *B
Page 8 of 23
Switching Characteristics Over the Operating Range[14]
Parameter
Description
CY7C056V
CY7C057V
Unit
-12
-15
-20
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
12
15
20
ns
tOHA
Output Hold From Address Change
3
3
3
ns
tACE[3, 15]
CE LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
8
10
12
ns
tLZOE[3, 16, 17, 18] OE Low to Low Z
0
0
0
ns
tHZOE[3, 16, 17, 18] OE HIGH to High Z
10
10
12
ns
tLZCE[3, 14, 17, 18] CE LOW to Low Z
3
3
3
ns
tHZCE[3, 16, 17, 18] CE HIGH to High Z
10
10
12
ns
tLZBE
Byte Enable to Low Z
3
3
3
ns
tHZBE
Byte Enable to High Z
10
10
12
ns
tPU[3, 18]
CE LOW to Power-Up
0
0
0
ns
tPD[3, 18]
CE HIGH to Power-Down
12
15
20
ns
tABE[15]
Byte Enable Access Time
12
15
20
ns
Write Cycle
tWC
Write Cycle Time
12
15
20
ns
tSCE[3, 15]
CE LOW to Write End
10
12
15
ns
tAW
Address Valid to Write End
10
12
15
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[15]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
10
12
15
ns
tSD
Data Set-Up to Write End
10
10
15
ns
tHD
Data Hold From Write End
0
0
0
ns
tHZWE[17, 18]
R/W LOW to High Z
10
10
12
ns
tLZWE[17, 18]
R/W HIGH to Low Z
3
3
3
ns
tWDD[19]
Write Pulse to Data Delay
25
30
45
ns
tDDD[19]
Write Data Valid to Read Data Valid
20
25
30
ns
Busy Timing[20]
tBLA
BUSY LOW from Address Match
12
15
20
ns
tBHA
BUSY HIGH from Address Mismatch
12
15
20
ns
tBLC
BUSY LOW from CE LOW
12
15
20
ns
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 10-pF load capacitance.
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Read Timing with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
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