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CY7C144-15AXC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C144-15AXC
Description  8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C144-15AXC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C144
CY7C145
Document #: 38-06034 Rev. *C
Page 7 of 20
tSD
Data Set-Up to Write End
10
15
15
25
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[11,12]
R/W LOW to High Z
10
15
20
25
ns
tLZWE[11,12]
R/W HIGH to Low Z
3
3
3
3
ns
tWDD[13]
Write Pulse to Data Delay
30
50
60
70
ns
tDDD[13]
Write Data Valid to Read Data
Valid
25
30
35
40
ns
BUSY TIMING[14]
tBLA
BUSY LOW from Address
Match
15
20
20
30
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
30
ns
tBLC
BUSY LOW from CE LOW
152020
30
ns
tBHC
BUSY HIGH from CE HIGH
15
20
20
30
ns
tPS
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
30
ns
tBDD
BUSY HIGH to Data Valid
15
25
35
55
ns
INTERRUPT TIMING[14]
tINS
INT Set Time
15
25
25
35
ns
tINR
INT Reset Time
15
25
25
35
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE
or SEM)
10
10
15
20
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
5
ns
tSPS
SEM Flag Contention
Window
55
55
ns
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
Switching Characteristics Over the Operating Range[9] (continued)
Parameter
Description
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.


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