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CY7C056V
CY7C057V
Document #: 38-06055 Rev. *B
Page 9 of 23
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE)[3] must be held HIGH during data
retention, within VDD to VDD – 0.2V.
2. CE must be kept between VDD – 0.2V and 70% of VDD
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VDD reaches the
minimum operating voltage (3.15 volts).
Notes:
21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VDD, Vin = VSS to VDD, TA = 25°C. This parameter is guaranteed but not tested.
Busy Timing[20]
tBHC
BUSY HIGH from CE HIGH
12
15
20
ns
tPS
Port Set-Up for Priority
5
5
5
ns
tWB
R/W LOW after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
11
13
15
ns
tBDD[21]
BUSY HIGH to Data Valid
12
15
20
ns
Interrupt Timing[20]
tINS
INT Set Time
12
15
20
ns
tINR
INT Reset Time
12
15
20
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)10
10
10
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
tSAA
SEM Address Access Time
12
15
20
ns
Switching Characteristics Over the Operating Range[14] (continued)
Parameter
Description
CY7C056V
CY7C057V
Unit
-12
-15
-20
Min.
Max.
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[22]
Max.
Unit
ICCDR1
@ VDDDR = 2V
50
µA
Data Retention Mode
3.15V
3.15V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
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