RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document Number: 38-07271 Rev. *C
Page 7 of 11
tLOCK
PLL lock time from power up
–
10
–
10
ms
tRELOCK1
PLL relock time (from same frequency, different phase) with
stable power supply
–500–500
μs
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply[17]
–
1000
–
1000
μs
tODCV
Output duty cycle deviation from 50%[11]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%[18]
–1.5
–
1.5
ns
tPWL
Output LOW time deviation from 50%[18]
–2.0
–
2.0
ns
tPDEV
Period deviation when changing from reference to reference[19]
–
0.025
–
0.025
UI
tOAZ
DIS[1:2] HIGH to output high impedance from ACTIVE[12, 20]
1.0101.0
10
ns
tOZA
DIS[1:2] LOW to output ACTIVE from output is high
impedance[20, 21]
0.5140.5
14
ns
AC Test Loads and Waveform
See note. [22]
Notes
17. fNOM must be within the frequency range defined by the same FS state.
18. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period.
20. Measured at 0.5V deviation from starting voltage.
21. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz.
22. These figures are for illustration only. The actual ATE loads may vary.
Switching Characteristics
Over the Operating Range[7, 8, 9, 10, 11] (continued)
Parameter
Description
CY7B9930/40V-2
CY7B9930/40V-5
Unit
Min.
Max.
Min.
Max.
2.0V
0.8V
3.3V
GND
2.0V
0.8V
3.3V
OUTPUT
(a) LVTTL AC Test Load
< 1ns
< 1 ns
(b) TTL Input Test Waveform
R1
R2
CL
R1 = 910
Ω
R2 = 910Ω
CL <30 pF
(Includes fixture and
probe capacitance)
R1 = 100
Ω
R2 = 100
Ω
CL < 25 pF up to 185 MHz
For LOCK output only
For all other outputs
10 pF from 185 to 200 MHz
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