16K x 16/18 Dual-Port Static RAM
CY7C026A
CY7C036A
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-06046 Rev. *C
Revised September 6, 2005
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• 16K x 16 organization (CY7C026A)
• 16K x 18 organization (CY7C036A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pb-Free packages available
Notes:
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
4. BUSY is an output in master mode and an input in slave mode.
R/WL
OEL
I/O8/9L–I/O15/17L
I/O
Control
Address
Decode
A0L–A13L
CEL
OEL
R/WL
BUSYL
I/O
Control
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
UBL
LBL
I/O0L–I/O7/8L
R/WR
OER
I/O8/9L–I/O15/17R
CER
UBR
LBR
I/O0L–I/O7/8R
UBL
LBL
Logic Block Diagram
A0L–A13L
True Dual-Ported
RAM Array
A0R–A13R
CER
OER
R/WR
BUSYR
SEMR
INTR
UBR
LBR
Address
Decode
A0R–A13R
[2]
[2]
[3]
[3]
[4]
[4]
14
8/9
8/9
14
8/9
8/9
14
14
CY7C026A
CY7C036A16K x 16/18 Dual-Port Static RAM