RoboClockII™ Junior,
CY7B9930V, CY7B9940V
High Speed Multifrequency
PLL Clock Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 38-07271 Rev. *C
Revised August 8, 2007
Features
■ 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
input/output operation
■ Matched pair output skew < 200 ps
■ Zero input-to-output delay
■ 10 LVTTL 50% duty-cycle outputs capable of driving 50ω
terminated lines
■ Commercial temperature range with eight outputs at 200
MHz
■ Industrial temperature range with eight outputs at 200 MHz
■ 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot
insertable reference inputs
■ Multiply ratios of (1–6, 8, 10, 12)
■ Operation up to 12x input frequency
■ Individual output bank disable for aggressive power
management and EMI reduction
■ Output high impedance option for testing purposes
■ Fully integrated PLL with lock indicator
■ Low cycle-to-cycle jitter (<100 ps peak-peak)
■ Single 3.3V ± 10% supply
■ 44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency
PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
Ten configurable outputs can each drive terminated transmission
lines with impedances as low as 50
Ω while delivering minimal and
specified output skews at LVTTL levels. The outputs are arranged
in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
these ten outputs can be connected to the feedback input as well
as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
primary clock source is not in operation. The reference inputs are
configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
and simplifies board layout.
3
3
3
3
FS
Output_Mode
FBDS0
FBDS1
DIS2
DIS1
QFA0
QFA1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
LOCK
FBKA
REFA+
REFA–
REFB+
REFB–
REFSEL
Divide
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide
Generator
Feedback Bank
Bank 2
Bank 1
Matrix
Block Diagram
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