Differential Clock Buffer/Driver
DDR400/PC3200-Compliant
CY2SSTV857-32
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07557 Rev. *E
Revised January 12, 2005
Features
• Operating frequency: 60 MHz to 230 MHz
• Supports 400-MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of –40°C to 85°C
• Conforms to JEDEC DDR specification
Description
The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
clocks in high-speed applications. The CY2SSTV857-32
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
features differential feedback clock outpts and inputs. This
allows the CY2SSTV857-32 to be used as a zero delay buffer.
When used as a zero delay buffer in nested clock trees, the
CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
Block Diagram
Pin Configuration
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
32
33
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
Y5
Y5#
Y6
Y6#
Y7
Y7#
Y8
Y8#
Y9
Y9#
FBOUT
FBOUT#
Test and
Powerdown
Logic
PLL
13
14
36
35
FBIN
FBIN#
CLK
CLK#
AVDD
37
16
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VS S
Y0#
Y0
VDDQ
Y1
Y1#
VS S
VS S
Y2#
Y2
VDDQ
VDDQ
CLK
CLK #
VDDQ
AVD D
AVS S
VS S
Y3#
Y3
VDDQ
Y4
Y4#
VS S
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VS S
Y5#
Y5
VDDQ
Y6
Y6#
VS S
VS S
Y7#
Y7
VDDQ
PD #
FB IN
FB IN #
VDDQ
FB O U T #
FB O U T
VS S
Y8#
Y8
VDDQ
Y9
Y9#
VS S
48 TSSOP Package
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