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CY7B995ACT Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7B995ACT
Description  2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B995ACT Datasheet(HTML) 4 Page - Cypress Semiconductor

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RoboClock®, CY7B995
Document #: 38-07337 Rev. *D
Page 4 of 13
Table 3. Feedback Divider Settings
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in Table 4 and
Table 5, respectively.
Table 4. Output Divider Settings – Bank 3
Table 5. Output Divider Settings – Bank 4
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in Table 6.
Table 6. Output Frequency Settings.
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that corre-
sponds to each FS level is given in Table 7.
Table 7. Frequency Range Select
Selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the tU value is: tU = 1 / (fNOM x MF)
where MF is a multiplication factor which is determined by the FS
setting as indicated in Table 8.
Table 8. MF Calculation
Table 9. Output Skew Settings
DS[1:0]
N-Feedback Input
Divider
Permitted Output Divider
Connected to FB
LL
2
1 or 2
LM
3
1
LH
4
1,2 or 4
ML
5
1 or 2
MM
1
1,2 or 4
MH
6
1 or 2
HL
8
1 or 2
HM
10
1
HH
12
1
3F[1:0]
K - Bank3 Output Divider
LL
2
HH
4
Other[5]
1
4F[1:0]
M- Bank4 Output Divider
LL
2
Other[5]
1
Configuration
Output Frequency
FB Input
Connected to
1Q[0:1] and
2Q[0:1]
[6]
3Q[0:1]
4Q[0:1]
1Qn or 2Qn
(N / R) x FREF (N / R) x (1 /
K) x FREF
(N / R) x (1 /
M) x FREF
3Qn
(N / R) x K x
FREF
(N / R) x FREF (N / R) x (K /
M) x FREF
4Qn
(N / R) x M x
FREF
(N / R) x (M /
K) x FREF
(N / R) x FREF
FS
PLL Frequency Range
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
FS
MF
fNOM at which tU is 1.0 ns (MHz)
L
32
31.25
M16
62.5
H8
125
nF[1:0]
Skew
(1Q[0:1],2Q[0:1])
Skew
(3Q[0:1])
Skew
(4Q[0:1])
LL[7]
–4tU
Divide By 2
Divide By 2
LM
–3tU
–6tU
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1tU
+2tU
+2tU
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide By 4
Inverted[8]
Configuration
Output Frequency
FB Input
Connected to
1Q[0:1] and
2Q[0:1]
[6]
3Q[0:1]
4Q[0:1]
Notes
5. These states are used to program the phase of the respective banks. See Table 8 and Table 9.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See Table 7.
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