Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

t

HZR

HIGH to TRI-STATE

Delay

Figure 14

Rout(0-9)

2.8

10

ns

t

LZR

LOW to TRI-STATE

Delay

2.8

10

ns

t

ZHR

TRI-STATE to HIGH

Delay

4.2

10

ns

t

ZLR

TRI-STATE to LOW

Delay

4.2

10

ns

t

DSR1

Deserializer PLL Lock

Time from PWRDWN

(with SYNCPAT)

Figure 15

Figure 16

(Note 7)

20MHz

1.7

3.5

µs

80MHz

1.0

2.5

µs

t

DSR2

Deserializer PLL Lock

time from SYNCPAT

20MHz

0.65

1.5

µs

80MHz

0.29

0.8

µs

t

ZHLK

TRI-STATE to HIGH

Delay (power-up)

LOCK

3.7

12

ns

t

Right

Figure 20

VCC = 3.15 to 3.6V

80MHz

+335

ps

VCC = 3.0V

+215

20MHz

+1

ns

t

RNMI-L

Ideal Noise Margin Left

Figure 20

VCC = 3.15 to 3.6V

80MHz

-395

ps

VCC = 3.0V

-520

20MHz

-1

ns

SCAN Circuitry Timing Requirements

Symbol

Parameter

Conditions

Min

Typ

Max

Units

f

MAX

Maximum TCK Clock

Frequency

R

Ω,C

25.0

50.0

MHz

t

S

TDI to TCK, H or L

1.0

ns

t

H

TDI to TCK, H or L

2.0

ns

t

S

TMS to TCK, H or L

2.5

ns

t

H

TMS to TCK, H or L

1.5

ns

t

W

TCK Pulse Width, H or L

10.0

ns

t

W

TRST Pulse Width, L

2.5

ns

t

REC

Recovery Time, TRST to

TCK

2.0

ns

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,

∆VOD,

VTH and VTL which are differential voltages.

Note 5: Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.

Note 7: For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and with specific

time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before

not receiving data to receiving synchronization patterns (SYNCPATs).

Margin is Guaranteed By Design (GBD) using statistical analysis.

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