MT48LC64M4A2_99 datasheet(18/77 Pages) MICRON

Part #	MT48LC64M4A2

Description	Synchronous DRAM 256Mb: x4, x8, x16 SDRAM

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Manufacturer	MICRON [Micron Technology]

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256MSDRAM_2.fm - Rev. L 10/07 EN

18

256Mb: x4, x8, x16 SDRAM

Functional Description

Figure 7:

Mode Register Definition

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed BL applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;

when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-

location (nonburst) accesses.

M3 = 0

1

2

4

8

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Operating Mode

Standard Operation

All other states reserved

0

–

0

–

Defined

–

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2

3

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Length

CAS Latency

BT

A9

A7

A6

A5

A4

A3

A8

A2

A1

A0

Mode Register (Mx)

Address Bus

9

7

65

4

3

8

2

1

0

M1

0

1

0

1

M2

0

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

1

0

1

M6

0

1

M6-M0

M8

M7

Op Mode

A10

A11

10

11

Reserved

WB

0

1

Write Burst Mode

Programmed Burst Length

Single Location Access

M9

Program

BA1, BA0 = “0, 0”

to ensure compatibility

with future devices.

A12

12

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