1:10 Clock Fanout Buffer
CY2CC810
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07056 Rev. *E
Revised September 5, 2006
Features
• Low-voltage operation
•VDD range from 2.5V to 3.3V
• 1:10 fanout
• Over voltage tolerant input hot swappable
• Drives either a 50-Ohm or 75-Ohm transmission line
• Low-input capacitance
• 250 ps typical output-to-output skew
• 19 ps typical DJ jitter
• Typical propagation delay < 3.5 ns
• High-speed operation > 500 MHz
• Industrial versions available
• Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type
outputs
dynamically
adjust
for
variable
impedance matching and reduce noise overall.
.
Block Diagram
Pin Configuration
OUTPUT
(AVCMOS)
IN
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q10
GND
VDD
INPUT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
Pin Description
Pin Number
Pin Name
Description
1
IN
Input
LVCMOS
2, 6, 10, 13, 17
GND
Ground
Power
4, 8, 15, 20
VDD
Power Supply
Power
3, 5, 7, 9, 11, 12, 14, 16, 18, 19
Q1... Q10
Output
AVCMOS
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