IMIC9530CT datasheet(1/11 Pages) CYPRESS

Part #	IMIC9530CT

Description	PCIX I/O System Clock Generator with EMI Control Features

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Manufacturer	CYPRESS [Cypress Semiconductor]

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PCIX I/O System Clock Generator with EMI

Control Features

C9530

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document #: 38-07033 Rev. *C

Revised October 31, 2005

Features

• Dedicated clock buffer power pins for reduced noise,

crosstalk and jitter

• Input clock frequency of 25 MHz to 33.3 MHz

• Output frequencies of XINx1, XINx2, XINx3 and XINx4

• Output grouped in two banks of five clocks each

• One REF XIN clock output

• SMBus clock control interface for individual clock

disabling and SSCG control and individual back

frequency selection

• Output clock duty cycle is 50% (± 5%)

• < 250 ps skew between output clocks within a bank

• Output jitter < 250 psec (175 psec with all outputs at the

same frequency)

• Spread Spectrum feature for reduced electromagnetic

interference (EMI)

• OE pins for entire output bank enable control and

testability

• 48-pin SSOP and TSSOP packages

Note:

1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state

REF.

Table 1. Test Mode Logic Table[1]

Input Pins

Output Pins

OEA

SA1

SA0

CLKA

REF

OEB

SB1

SB0

CLKB

HIGH

LOW

XIN

HIGH

LOW

HIGH

2 * XIN

XIN

HIGH

LOW

3 * XIN

XIN

HIGH

4 * XIN

XIN

LOW

X

Three-state

Block Diagram

Pin Configuration

XIN

CLKB4

CLKB3

CLKB2

CLKB1

CLKB0

OEB

CLKA3

CLKA2

CLKA1

CLKA0

/N

SSCG#

CLKA4

SSCG

Logic

/N

1

0

XOUT

I2C

Control

Logic

SCLK

OEA

IA(0:2)

AGOOD#

BGOOD#

REF

SDATA

SA(0,1)

SB(0,1)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

XIN

VDD

XOUT

VSS

SA1

VSS

CLKA0

VDDA

CLKA2

VSS

VDDA

CLKA4

VSS

CLKA1

AGOOD#

VSS

IA1

IA2

AVDD

OEA

OEB

VSS

SSCG#

VSS

AVDD

BGOOD#

AVDD

CLKB4

VDDB

VSS

VDDB

CLKB1

VSS

SB1

VSS

CLKB3

CLKB2

CLKB0

SB0

VDD

VSS

VDD

SCLK

SDATA

IA0

REF

41

42

43

44

45

46

47

48

SA0

CLKA3

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