FUNCTIONAL DESCRIPTION

The U511 is a PWM quad low side driver for in-

ductive loads. The duty cycle of the internal gen-

erated PWM signal is set by a microcontroller via

a serial interface for each output. An output slope

limitation for both dv/dt and di /dt is implemented

to reduce RFI. The PWM generation is realized

avoiding a simultaneous output switching. As a

result, di/dt becomes smaller. Integrated flyback

diodes clamp the output voltage during the fly-

back phase of the low side switches.

The driver is protected against short circuit. An

undervoltage shutdown circuit switches off all out-

voltage all outputs remain in off state regardless

of the input state. After each malfunction which

resets the driver, only the serial link interface can

reactivate the normal function. In case of overcur-

the output off. The overcurrent information can be

read via the serial link for each driver separately

at the negative edge of the corresponding PWM

signal.

The interface to the microcontroller is realized

with a 16 bit synchronous serial peripheral inter-

face (SPI). If CS is switched low, the serial link

becomes active and SDO goes to low impedance.

At the rising edge of the SCLK signal, one of the

16 bit of data stored in a shift register appear se-

quencely at SDO. These data contain the 8 error

flags, the status of thermal diagnostic flag and the

external reset sources RES1, RES2 and the over-

current flgs c1...c4. The last bit is framing infor-

mation (see fig. 7). At each falling edge of SCLK,

one of the 16 bits of data sent by the microcon-

troller is transferred via the SDI input to the driver.

These data contain the duty-cycle information for

the internal PWM generation (4 times 4 bit).

On the rising edge of CS the previously stored in-

formation is transferred to the circuits. SDO be-

come now high impedance and SDI is inactive.

The serial interface of the QLSD is cascadable

with the serial link interface of another QLSD,

thus obtaining a 32 bit serial link information wich

can control eight inductive loads. For a safety

data transfer the takeover of data bits is only real-

ized when the number of SCLK - clocks is n x 16

(n

≥ 1).

The PWM duty cycle is set by 4 bit for each out-

put independently via the serial link. If all four bits

for an output are zero, the output is turned off, but

the error diagnosis will work correctly (see fig. 5

and 6). The PWM frequency is defined by an ex-

ternal capacitor on the OSC pin. Rext defines

through the reference current the output current

slope, the diagnostic current sink and the internal

For error diagnosis the voltage on the output is

measured during the on and off state of the par-

ticular output driver. Upon the rising edge of the

PWM signal (at this moment the power output is

off and will be switched on) the status of COMP1

is stored into an internal latch. On the falling edge

of the PWM signal ( the power output is on and

will be switched off) the status of COMP2 is

stored into another internal latch. This information

can be read via the serial link for each output

driver separately (see fig. 7).

The thermal diagnostic switch the thermal flag to

0 in case of overtemperature T

To avoid male functions due to extensive noise or

be blocked externally via capacitors.

L9341

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