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X9520 Datasheet(PDF) 3 Page - Intersil Corporation

Part # X9520
Description  Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X9520 Datasheet(HTML) 3 Page - Intersil Corporation

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3
FN8206.2
August 20, 2007
Pinout
X9520
(20 LD TSSOP)
TOP VIEW
V2
RL2
RH0
3
4
V1/VCC
SCL
RW0
RL0
RW1
RH1
7
8
V3
VSS
10
RL1
RH2
1
18
19
17
20
14
15
13
16
12
11
MR
6
RW2
2
SDA
9
V3RO
5
WP
V1RO
V2RO
NOT TO SCALE
Pin Descriptions
TSSOP
NAME
FUNCTION
1RH2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2Rw2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3RL2
Connection to other end of resistor array for (the 256 Tap) DCP 2.
4
V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the
VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used.
5
V3RO
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than VTRIP3 and goes LOW
when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”
resistor.
6
MR
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin
(V1/VCC RESET Output pin). V1RO will remain HIGH for time tpurst after MR has returned to it’s normally LOW state. The
reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
7
WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock
feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed
in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin
uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
8
SCL
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
9
SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input
buffer is always active (not gated). This pin requires an external pull up resistor.
10
Vss
Ground.
11
RL1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
Rw1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
RH1
Connection to end of resistor array for (the 100 Tap) DCP 1.
14
RH0
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
15
RW0
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
RL0
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17
V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the
VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used.
18
V2RO
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than VTRIP2, and goes LOW
when V2 is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an
external “pull-up” resistor.
X9520


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