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L6926D Datasheet(PDF) 5 Page - STMicroelectronics

Part # L6926D
Description  HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6926D Datasheet(HTML) 5 Page - STMicroelectronics

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L6926D
Low Noise Mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode
can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode
in very light load conditions but for medium-high load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load
conditions, the device could skip some cycles in order to keep the output voltage in regulation.
Synchronization
The device can also be synchronized with an external signal from 500KHz up to 1.4MHz.
In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very
light load conditions.
The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the
protections effective (see relative sections).
Short Circuit Protection
During the device operation, the inductor current increases during the high side turn on phase and decrease
during the high side turn off phase based on the following equations:
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ∆ION increases
and
∆IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off
and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible ∆ION.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the
TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This
protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher
that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the
inductor current down to this threshold.
So, the maximum peak current in worst case conditions will be:
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
Slope Compensation
In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-
by-pulse instability (the so called sub harmonic oscillation) can occur.
To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the
current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP
pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage
(due to the increased current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases.
∆I
ON
V
IN
V
OU T
()
L
----------------------------------- T
ON
=
∆I
OF F
V
OUT
()
L
------------------- T
OFF
=
I
P EAK
I
VAL LEY
V
IN
L
--------- T
ON _MIN
+
=


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