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L6918DTR Datasheet(PDF) 3 Page - STMicroelectronics |
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L6918DTR Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 35 page 3/35 L6918 L6918A ABSOLUTE MAXIMUM RATINGS THERMAL DATA Symbol Parameter Value Unit Vcc, VCCDR To PGND 15 V VBOOT-VPHASE Boot Voltage 15 V VUGATE1-VPHASE1 VUGATE2-VPHASE2 15 V LGATE1, PHASE1, LGATE2, PHASE2 to PGND -0.3 to Vcc+0.3 V VID0 to VID4 -0.3 to 5 V All other pins to PGND -0.3 to 7 V VPHASEx Sustainable Peak Voltage t<20nS @ 600kHz 26 V Symbol Parameter Value Unit Rth j-amb Thermal Resistance Junction to Ambient 60 °C / W Tmax Maximum junction temperature 150 °C Tstorage Storage temperature range -40 to 150 °C Tj Junction Temperature Range 0 to 125 °C PMAX Max power dissipation at Tamb=25 °C 2W L6918A (MASTER) PIN FUNCTION N. Name Description 1 LGATE1 Channel 1 low side gate driver output. 2 VCCDR LS Mosfet driver supply. 5V or 12V buses can be used. 3 PHASE1 This pin is connected to the Source of the upper mosfet and provides the return path for the high side driver of channel 1. 4 UGATE1 Channel 1 high side gate driver output. 5 BOOT1 Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot). 6 VCC Device supply voltage. The operative supply voltage is 12V. 7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground. 8 COMP This pin is connected to the error amplifier output and is used to compensate the control feedback loop. 9 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50 µA at full load, 70µA at the Over Current threshold). Connecting a resistor RFB between this pin and VSEN pin allows programming the droop effect. 10 VPROG_OUT Reference voltage output used for voltage regulation. This pin must be connected together with the slave device VPROG_IN pin. Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed). 11 SYNC_OUT Synchronization output signal. From this pin exits a square - 50% duty cycle - 5Vpp –90 deg phase shifted wave clock signal that the Slave device PLL locks to. Connect this pin to the Slave SYNC_IN pin. 12 SLAVE_OK Open-drain input/output used for start-up and to manage protections as shown in the timing diagram. Internally pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF capacitor vs. SGND. |
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