ASAHI

[AK2358FI

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Signal Reception

FSL set to “O”.

N

= “1”

I

FSL set to “ 1”

N

Reception data read i

Set so that a

detection signal (FD) is put out

the

pin .

Synchronization frame detection ?

: Reception voice u ut e

Set so that an

signal reception flag

is put ou t

the

pin .

Reception of 8 bit of data ?

: Reading of 8 bit of data. change to

I

FCLN set to “O”

I

fram e

I

I

A

is “O”, the internal nodes RDATA, RCLK are fixed to

“l”.

After a synchronization frame is detected, FD goes to “L” during the period “T”, then

FCLN is set to “l”.

RDATA and RCLK put out the data following to the synchronized frame pattern, and these

are stored in the internal buffer.

After 8 bit of reception data have been entered to the internal buffer, RDF goes “L”.

After the CPU detect that RDF is “L”, it puts out 8

bits to SCLK, then read 8

bit of reception data from the SDATA pin.

input of 8

bits

SCLK, RDF goes “H”.

Afterwards,

repeating the steps (4) and (5) the necessary data bits are read.

After the necessary data have been read, DIR goes “H”,

is set to “O”

the

serial interface,

internal nodes RDATA and RCLK are set to “l”, then

system

waits for

synchronization frame.

0152-E-00

-20 ”

1996/12