CAT9555_08 datasheet(10/17 Pages) CATALYST

Part #	CAT9555

Description	16-bit I2C and SMBus I/O Port with Interrupt

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Manufacturer	CATALYST [Catalyst Semiconductor]

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10 / 17 page

CAT9555

10

Doc. No. MD-9003 , Rev. G

Characteristics subject to change without notice

Figure 7. Acknowledge Timing

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data. The SDA line remains stable LOW during the

HIGH period of the acknowledge related clock pulse

(Figure 7).

The CAT9555 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write operation,

it responds with an acknowledge after receiving each

data byte.

When the CAT9555 begins a READ mode it transmits

8 bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge, the CAT9555 will continue to transmit

data. If no acknowledge is sent by the Master, the

device terminates data transmission and waits for a

STOP condition. The master must then issue a stop

condition to return the CAT9555 to the standby power

mode and place the device in a known state.

Registers and Bus Transactions

The CAT9555 internal registers and their address and

function are shown in Table 1.

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

register command byte acts as a pointer to determine

which register will be written or read.

The input port register is a read only port. It reflects the

incoming logic levels of the I/O pins, regardless of

whether the pin is defined as an input or an output by the

configuration register. Writes to the input port register

are ignored.

18

9

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK DELAY (

≤ tAA)

ACK SETUP (

≥ tSU:DAT)

Table 1. Register Command Byte

Table 3. Registers 2 and 3 – Output Port Registers

Table 2. Registers 0 and 1 – Input Port Registers

Table 4. Registers 4 and 5 – Polarity Inversion

Registers

Table 5. Registers 6 and 7 – Configuration Registers

)

x

e

h

(

d

n

a

m

o

Cr

e

t

s

i

g

e

R

h

00

t

r

o

P

t

u

p

n

I

h

11

t

r

o

P

t

u

p

n

I

h

20

t

r

o

P

t

u

p

t

u

O

h

31

t

r

o

P

t

u

p

t

u

O

h

40

t

r

o

P

n

o

i

s

r

e

v

n

I

y

t

i

r

a

l

o

P

h

51

t

r

o

P

n

o

i

s

r

e

v

n

I

y

t

i

r

a

l

o

P

h

60

t

r

o

P

n

o

i

t

a

r

u

g

i

f

n

o

C

h

71

t

r

o

P

n

o

i

t

a

r

u

g

i

f

n

o

C

t

i

b

7

.

0

O6

.

0

O5

.

0

O4

.

0

O3

.

0

O2

.

0

O1

.

0

O0

.

0

O

t

l

u

a

f

e

d

11

1

11

t

i

b

7

.

1

O6

.

1

O5

.

1

O4

.

1

O3

.

1

O2

.

1

O1

.

1

O0

.

1

O

t

l

u

a

f

e

d

11

1

11

t

i

b

7

.

0

N6

.

0

N5

.

0

N4

.

0

N3

.

0

N2

.

0

N1

.

0

N0

.

0

N

t

l

u

a

f

e

d

0

0000

0

t

i

b

7

.

1

N6

.

1

N5

.

1

N4

.

1

N3

.

1

N2

.

1

N1

.

1

N0

.

1

N

t

l

u

a

f

e

d

0

0000

0

t

i

b

7

.

0

C6

.

0

C5

.

0

C4

.

0

C3

.

0

C2

.

0

C1

.

0

C0

.

0

C

t

l

u

a

f

e

d

1

1111

1

t

i

b

7

.

1

C6

.

1

C5

.

1

C4

.

1

C3

.

1

C2

.

1

C1

.

1

C0

.

1

C

t

l

u

a

f

e

d

1

1111

1

t

i

b

7

.

O

I6

.

O

I5

.

O

I4

.

O

I3

.

O

I2

.

O

I1

.

O

I0

.

O

I

t

l

u

a

f

e

d

XX

X

XX

t

i

b

7

.

1

I6

.

1

I5

.

1

I4

.

1

I3

.

1

I2

.

1

I1

.

1

I0

.

1

I

t

l

u

a

f

e

d

XX

X

XX

The default value 'X' is determined by the externally

applied logic lavel

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