Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with vectors is compiled. Once downloaded, the JEDEC

file preload sequence will be done automatically by most

of the approved programmers after the programming.

Power Up Reset

The registers in the ATF16V8Bs are designed to reset dur-

result, the registered output state will always be high on

power-up.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the un-

lowing conditions are required:

2) After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and

Pin Capacitance

(f = 1 MHz, T = 25°C)

(1)

Typ

Max

Units

Conditions

58

pF

68

pF

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF16V8B fuse patterns. Once programmed, fuse

verify and preload are inhibited. However, the 64-bit User

Signature remains accessible.

The security fuse should be programmed last, as its effect

is immediate.

Parameter Description

Typ

Max

Units

Power-Up

Reset Time

600

1,000

ns

Power-Up

Reset

Voltage

3.8

4.5

V

Input Test Waveforms and

Measurement Levels:

Commercial

Output Test Loads:

ATF16V8B

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