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FN6088.5

July 31, 2007

During an overvoltage transient event, such as occurs during

system level IEC 61000 ESD testing, substrate currents can

be generated in the IC that can trigger parasitic SCR

structures to turn ON, creating a low impedance path from

the V+ power supply to ground. This will result in a

significant amount of current flow in the IC which can

potentially create a latch-up state or permanently damage

the IC. The external V+ resistor limits the current during this

over-stress situation and has been found to prevent latch-up

or destructive damage for many overvoltage transient

events.

the IC produces an insignificant voltage drop across the

100

Ω series resistor resulting in no impact to switch

operation or performance.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 9). To prevent forward biasing these diodes, V+ must

be applied before any input signals and the input signal

voltages must remain between V+ and GND.

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provide additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Logic inputs can easily be protected by adding a 1k

Ω

resistor in series with the input (see Figure 9). The resistor

limits the input current below the threshold that produces

permanent damage and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

diodes to the signal pins as shown in Figure 9 will shunt the

fault current to the supply or to ground thereby protecting the

switch. These Schottky diodes must be sized to handle the

expected fault current.

.

Power-Supply Considerations

The ISL84684 construction is typical of most single supply

CMOS analog switches, in that they have two supply pins:

V+ and GND. V+ and GND drive the internal CMOS

switches and set their analog voltage limits. Unlike switches

with a 4V maximum supply voltage, the ISL84684 5.5V

maximum supply voltage provides plenty of room for the

10% tolerance of 4.3V supplies, as well as room for

overshoot and noise spikes.

The minimum recommended supply voltage is 1.65V. It is

important to note that the input signal range, switching times,

and ON-resistance degrade at lower supply voltages. Refer

to the “Electrical Specification” tables on page 2 and “Typical

Performance Curves” on page 9 for details.

V+ and GND also power the internal logic and level shiftiers.

The level shiftiers convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)

over a supply range of 2.7V to 4.5V (see Figure 18). At 2.7V,

CMOS guaranteed low output minimum level of 0.5V, but

noise margin is reduced.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

GND

V+

OPTIONAL

PROTECTION

RESISTOR

OPTIONAL

SCHOTTKY

DIODE

OPTIONAL

SCHOTTKY

DIODE

FIGURE 9. OVERVOLTAGE PROTECTION

ISL84684