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DS90LV048A Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DS90LV048A
Description  3V LVDS Quad CMOS Differential Line Receiver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS90LV048A Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Switching Characteristics (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHZ
Disable Time High to Z
R
L =2kΩ
814
ns
t
PLZ
Disable Time Low to Z
C
L =15pF
8
14
ns
t
PZH
Enable Time Z to High
(
Figure 3 and Figure 4)
9
14
ns
t
PZL
Enable Time Z to Low
914
ns
f
MAX
Maximum Operating Frequency (Note 14)
All Channels Switching
200
250
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: All typicals are given for: VCC = +3.3V, TA = +25˚C.
Note 4: Generator waveform for all tests unless otherwise specified:f=1 MHz, ZO =50Ω,tr and tf (0% to 100%) ≤ 3 ns for RIN.
Note 5: The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is not supported
over the common-mode range of 0V to 2.4V, but is supported only with inputs shorted and no external common-mode voltage applied. A VID up to VCC−0Vmay
be applied to the RIN+/RIN− inputs with the Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased
from 200mV to 400mV. Skew specifications apply for 200mV
≤ VID ≤ 800mV over the common-mode range .
Note 6: tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel
Note 7: tSKD2, Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with
any event on the inputs.
Note 8: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC,
and within 5˚C of each other within the operating temperature range.
Note 9: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max−Min| differential propagation delay.
Note 10: ESD Rating:HBM (1.5 k
Ω, 100 pF) ≥ 10kV
EIAJ (0
Ω, 200 pF) ≥ 1200V
Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature specification.
Note 12: CL includes probe and jig capacitance.
Note 13: VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range −0.2V to VCC− VID/2. However, to be compliant with
AC specifications, the common voltage range is 0.1V to 2.3V
Note 14: fMAX generator input conditions: tr =tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60/40% duty cycle,
VOL (max 0.4V), VOH (min 2.7V), Load = 15 pF (stray plus probes).
Parameter Measurement Information
10088803
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
10088804
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
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