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DS90LV047A Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DS90LV047A
Description  3V LVDS Quad CMOS Differential Line Driver
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90LV047A Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Typical Application (Continued)
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the
current mode driver switches a fixed current between its
output without any substantial overlap current. This is similar
to some ECL and PECL devices, but without the heavy static
I
CC requirements of the ECL/PECL designs. LVDS requires
> 80% less current than similar PECL devices. AC specifi-
cations for the driver are a tenfold improvement over other
existing RS-422 drivers.
The TRI-STATE function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
The DS90LV047A has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the
device easily allows for matching electrical lengths of the
differential pair trace lines between the driver and the re-
ceiver as well as allowing the trace lines to be close together
to couple noise as common-mode. Noise isolation is
achieved with the LVDS signals on one side of the device
and the TTL signals on the other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be < 10mm long). This will help eliminate
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will re-
sult. (Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber or vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
TERMINATION
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90
Ω and 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor ter-
mination. Typically, connecting a single resistor across the
pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10mm
(12mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100k
Ω), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100
Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise
reduction and signal quality. Balanced cables tend to gener-
ate less EMI due to field canceling effects and also tend to
pick up electromagnetic radiation a common-mode (not dif-
ferential mode) noise which is rejected by the receiver.
For cable distances < 0.5M, most cables can be made to
work effectively. For distances 0.5M
≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available
and relatively inexpensive.
LVDS FAIL-SAFE
This section addresses the common concern of fail-safe
biasing of LVDS interconnects, specifically looking at the
DS90LV047A driver outputs and the DS90LV048A receiver
inputs.
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
www.national.com
6


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